Class S amplifiers/modulators are used for both amplification and amplitude modulation of a signal, especially in radio frequency applications. The popularity of class S amplifiers/modulators is due, in part, to the high rate of efficiency possible using class S techniques, which in many cases is close to 100 percent. At least one example where the use of class S amplifiers/modulators has been previously effective is in narrowband applications. Narrowband applications are applications where the frequency range of the input signal is relatively limited.
However for some uses, where it is desirable to operate over a relatively wider range of input frequencies, including higher input and output frequencies, the effectiveness of circuits using class S amplifiers/modulators is diminished. One example of a use where the performance of circuits using class S amplifiers/modulators begins to degrade is their use in a code division multiple access (CDMA) power amplifier supply modulator of a cellular communication system.
In a CDMA power amplifier supply modulator, a class S amplifier/modulator would preferably be used to provide the DC power to a radio frequency power amplifier. In this environment the power amplifier stage is typically a class AB radio frequency amplifier.
FIG. 1 shows a block diagram 10 generally depicting an amplifier 12 for receiving a sinusoidal input signal 14 and producing an amplified output signal. In the preferred embodiment the amplifier corresponds to a class S amplifier/modulator 12, which includes a pulse width modulation circuit (PWM) 16 and a low pass filter 18.
FIG. 2 shows a circuit schematic 20 of an example of an output drive stage and low pass filter for a class S amplifier The output drive stage is part of the PWM circuit 16. The output drive stage includes a pair of transistors; 22 and 24 arranged in a totem pole configuration. The source of transistor 22 is coupled to the supply voltage 26 and the drain of transistor 22 is coupled to the source of transistor 24. The drain of transistor 24 is coupled to ground 28. The gates of transistors 22 and 24 are each coupled to separate drivers 30 and 32. The connection between the drain of transistor 22 and the source of transistor 24 forms an output of the output drive stage, which is coupled to the input of a low pass filter.
The low pass filter includes a pair of LC circuits, wherein the inductors 34 and 36 are coupled in series with the output signal path, and the capacitors 38 and 40 are coupled across the output signal path and ground 28.
The output drive stage produces a pulse modulated signal having a varying duty ratio. The low pass filter receives the pulse modulated signal and produces an output signal having a more slowly varying DC or average voltage component to appear at the output load.
The output drive stage, illustrated in FIG. 2, will generally operate efficiently for signals having a frequency up to 1 MHz, however for signals greater than 1 MHz, the efficiency of the output drive stage begins to significantly degrade.
An alternative output drive stage using class S techniques, capable of efficient operation for higher frequency signals, is provided for in FIG. 3. FIG. 3 shows a circuit schematic 42 of an output drive stage and low pass filter for a class S modulator.
The output drive stage and low pass filter 42 of FIG. 3 differs from the output drive stage and low pass filter 20 of FIG. 2, in that in place of the transistor 24, a commutating diode 44 is used. The commutating diode 44 has its anode coupled to the drain of transistor 22 and its cathode coupled to ground 28. Correspondingly the second driver 32 is not present. The output drive stage of FIG. 3, further includes a second diode 46 having its anode coupled to the supply voltage 26 and its cathode coupled to the drain of transistor 22 and the anode of the commutating diode 44, which corresponds to the output of the output drive stage and the input of the low pass filter.
A class S modulator having the output drive stage and low pass filter 42 of FIG. 3, is capable of efficiently operating at higher operating frequencies, however is much more sensitive to variations in the output impedance. The output drive stage of FIG. 3, experiences a degradation in performance when the output impedance exceeds approximately 10 times the average design load.
For a CDMA power amplifier supply modulator, as identified above, a class S amplifier/modulator would preferably be used as a DC power supply, for producing an output signal which would be used as the power supply input to a subsequent class AB radio frequency amplifier stage. The input impedance of a class AB amplifier provides an output load impedance for the class S amplifier/modulator which can be closely approximated as a current source 48, whose magnitude is proportional to the sum of the quiescent bias current plus the instantaneous envelope current. The current source 48 is shown in FIG. 1.
The input signal can be represented by the equation: EQU V.sub.in (t)=A cos(.omega..sub.m t)+V.sub.p (t)
Correspondingly, the output current which is proportional to the input signal can be represented by the equation: EQU i.sub.e (t)=b cos(.omega..sub.m t)+dc.sub.i
The output voltage can be represented by the equation: EQU V.sub.e (t)=a cos(.omega..sub.m t+.phi..sub.e (t))+dc.sub.v
wherein .phi..sub.e (t) represents the phase difference between the output current i.sub.e (t) and the output voltage v.sub.e (t), which results from the current source having an equivalent impedance Z.sub.Load, which includes both a real and a reactive component.
If Z.sub.Load were purely resistive, .phi..sub.e (t) would equal zero, and the output impedance would be relatively constant, allowing for the efficient use of the output drive stage and low pass filter 42, shown in FIG. 3. However in most instances .phi..sub.e (t) will not equal zero, and will result in an output impedance Z.sub.Load, which will vary over time. The output impedance Z.sub.Load is equal to the output voltage V.sub.e (t) divided by the output current i.sub.e (t).
As a function of time the output impedance Z.sub.Load is graphically, represented by graph 50, shown in FIG. 4. The spikes 52 represent the maximum value of the output impedance Z.sub.Load, which occurs when the output current i.sub.e (t) is approximately zero. The valleys 54 represent the minimum value of the output impedance Z.sub.Load, which occurs when the output voltage V.sub.e (t) is approximately zero. The output impedance Z.sub.Load often will vary by a factor greater than 10 times the average design load. As previously identified, the largely varying output impedance Z.sub.Load will interfere with the efficient operation of the class S modulator having the output drive stage and low pass filter, shown in FIG. 3. Therefore a load limiting circuit and method for limiting the output impedance seen by an amplifier would be beneficial.